The present invention relates in general to microprocessors, and in particular to operating system context switching.
As the master control program that runs the computer, the operating system (OS) periodically interrupts the user process to, for example, schedule tasks and manage resources. The interrupt is typically accomplished by having a clock interrupt every 1/100th of a second to query whether the operating system needs to do anything. As microprocessor clock speeds have increased, the amount of overhead and housekeeping done by the operating system has also increased, and thus the net percentage of time required for these operating system tasks has not been significantly reduced.
In addition to the increased amount of work done by the operating system, other factors have combined to increase the intrusion of the operating system on user programs. For example, the use of multi-tasking, where multiple programs are run in parallel with frequent context switches between them, requires more interruptions for the operating system to handle the context switch. In addition, processor clock speeds have increased much more dramatically than memory access speeds. Thus, memory accesses use up an increasingly larger number of processor cycles as the gap between processor clock speed and memory access speed increases. Context switches between an operating system and user programs, or between user programs, often require a number of memory accesses.
Context switching upon an interrupt to the operating system or a switch between tasks requires a number of tasks. In particular, the state of the necessary registers used by the execution unit need to be saved to memory. For a pipelined processor, instructions in the pipeline need to propagate through the pipeline to empty the pipeline before the context switch can occur. As the pipeline grows deeper, the length of time required for this correspondingly increases.
In addition, the operating system activities require operating system specific instructions and data which must be stored in the instruction and data caches. This not only consumes cache space that would otherwise be allocated to user applications, it would also cause the overwriting of user instructions and data, thus increasing the chances of a cache miss on a subsequent return to the user process. This effectively limits the available memory bandwidth for user applications.
User performance degradation caused by the OS context switch is a more severe problem in multi-processor systems. In such systems, a holdup by one processor due to OS activity may delay a group of other processors that are tightly synchronized over well defined workloads. The OS interferences with the user process creates user process inconsistency such that the same user program may take up different amounts of time to execute at different times. This inconsistency does not permit the operating system to efficiently schedule and distribute tasks among the various processors operating in parallel. Thus, programs that may take longer to execute are scheduled to run in parallel with smaller sized tasks, where the speed is limited by the slowest processor.
Another concern raised by OS context switching is OS security. In the existing processor architectures, the cache memory typically includes mixed user and OS spaces. After an OS interrupt occurs, the cache may contain sensitive OS data. A cache flush by a subsequent user may expose secure operations executed by the OS (e.g., decoding a password or a secure instruction) to a user process.
There is therefore a need to reduce or eliminate the loss of time and memory bandwidth to operating system overhead, to improve user process consistency, and to provide a more secure operating system.